(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to achieve global planarization for integrated circuits comprised with dynamic random access memory, (DRAM), devices, and with logic devices.
(2) Description of Prior Art
Integration of memory devices, such as DRAM devices, with logic devices, on the same semiconductor chip, have resulted in enhanced performance, as well as cost reductions, for the specific semiconductor chip formed with both type devices, when compared to counterpart combinations of semiconductor chips, each comprised with either only memory or only logic devices. In addition, the performance of DRAM devices has been enhanced via the use of crown shaped capacitor structures, resulting in increased capacitor surface area, thus supplying increased capacitance and signal. However the high step height of the DRAM, crown shaped capacitor, located in a memory cell array, adjacent to peripheral regions comprised with lower step height, logic devices, can lead to difficulties when attempting to globally cover these devices with insulator.
This invention will describe a novel procedure for obtaining global planarization for semiconductor chips comprised with both type devices, resulting in a smooth top surface topography for passivating insulator layers which overlay both DRAM devices, comprised with crown shaped capacitor structures, and logic devices, comprised with metal interconnect structures, less demanding in step height than the crown shaped capacitor structures, of the DRAM devices. This is accomplished using a series of selective HF vapor etch procedures. After formation of the crown shaped storage node structures, in storage node openings formed in a thick borophosphosilicate glass, (BPSG), layer, a thin, chemically vapor deposited, silicon oxide layer, formed using tetraethylorthosilicate, (TEOS), as a source, is used to cover the crown shaped storage node structures, as well as covering all regions of the top surface of the BPSG layer, including the region between crown capacitor shapes. A photoresist shape is formed overlying non-crown shaped structures, followed by a first HF vapor etch procedure, selectively removing the TEOS formed, silicon oxide layer from the crown capacitor shapes, as well as from the BPSG layer, located between the crown shaped structures. A second HF vapor etch is then used to remove the BPSG layer from between crown shaped structures, using either the photoresist shape as a mask, or removing the photoresist shape, and using the thin TEOS formed, silicon oxide layer, as an etch mask. The use of the TEOS formed silicon oxide layer, and the selective HF vapor etch, do not rely on the photoresist shape, which can be damaged during a conventional wet etch, BPSG removal procedure, to protect insulator layers overlying non-DRAM regions. Subsequent formation of polysilicon upper plate structures, fill the space between the crown shaped structures, resulting in a smooth top surface topography for a semiconductor device, comprised with high step height, DRAM devices, and with less severe step height, logic devices.
Prior art, such as Kleinhenz et al, in US. Pat. No. 5,876,879, as well as Man, in U.S. Pat. No. 5,376,233, describe methods of selectively etching insulator layers, using HF vapor etching. These prior arts however, do not describe the novel series of procedures, photoresist masking, TEOS formed silicon oxide masking, and the selective HF vapor etch, used in this invention, to obtain global planarization for semiconductor chips comprised with varying step height structures.